HERE YOU CAN GET ALL VLSI UPDATES.
Pages
(Move to ...)
HOME
PHYSICAL DESIGN CONCEPTS
LOW POWER TECHNIQUES
DFT
LOGIC SYNTHESIS
INTERVIEW QUESTIONS
ENCOUNTER COMMANDS
ABOUT ME
▼
(Move to ...)
Home
▼
Thursday, 30 November 2017
CONTENTS OF CTS SPEC
›
Clock information for which clock tree need to build NDR rules (double width and double spacing) Max clock cap limit Clock inverters a...
INPUTS AND OUTPUTS OF EACH STAGE
›
SYNTHESIS Input files required for synthesis RTL SDC .LIBS Output files of synthesis gate level netlist SDC PNR ...
2 comments:
DIFFERENT KIND OF CELLS
›
What are end cap cells ? End caps are the physical only cells which are used to identify the end of the standard cell rows...
Wednesday, 29 November 2017
QUESTIONS ON VLSI BASICS
›
QUESTIONS BASED ON FLOORPLANNING
›
What is core utilization ? It is the ratio of (std cell area + macro area + blockage area) / total area What is cell utilization ...
1 comment:
Monday, 27 November 2017
ENCOUNTER COMMANDS
›
To select all the ports in the design selectIOPin * To display all the contents in the shell window enc_tcl_re...
1 comment:
Sunday, 26 November 2017
QUESTIONS ON LOW POWER
›
What is isolation cell ? The cells which are used to isolate the output of the power down domain is called isolation cells. ...
›
Home
View web version