CONTENTS OF CTS SPEC

• Clock information for which clock tree need to build
• NDR rules (double width and double spacing)
• Max clock cap limit
• Clock inverters and buffers types
• Target skew
• Preferred routing layers
• Non leaf pin max tran
• Leaf pin max tran
• Max fanout
• Max delay
• Min delay

INPUTS AND OUTPUTS OF EACH STAGE

SYNTHESIS

Input files required for synthesis

• RTL
• SDC
• .LIBS

Output files of synthesis

• gate level netlist
• SDC

PNR

Input files required for PNR

• Gate level netlist
• sdc
• upf/cpf
• .libs
• .lefs
• captables

Outputs of PNR

• Gate level netlist
• sdc
• def
• lef
• database

EXTRACTION

Input files required for extraction

• .def
• qrc tech file

Outputs of extraction

• spef

CROSSTALK

Input files required for crosstalk

• netlist
• sdc
• spef

Outputs of crosstalk

• sdf

STA

Input files required for STA

• Netlist from PNR
• sdc
• .libs
• spef
• sdf
• .def
• .upf
• eco_spacing_rule file

Outputs of STA

• timing reports

LEC

Input files required for LEC

• golden netlist : netlist that we get from synthesis
• source netlist: netlist we got after PNR
• libs

Outputs for LEC

• comparison reports

DRC

Input files required for DRC

• GDS
• drc rule deck file

Outputs of DRC

• Reports

LVS

Input files required for LVS

• hcell
• cdl
• source netlist
• layout netlist

Outputs for LVS

• reports

DIFFERENT KIND OF CELLS

What are end cap cells ?

End caps are the physical only cells which are used to identify the end of the standard cell rows and used to identify the blocks in the chip. During fabrication process etching occurs and because of that cells present towards the end of the chip are etched. As the functional cells are etched during fabrication it may hamper the functionality of the standard cells. So generally we place end cap cells towards the boundary so that etching will not impact the functional cells.

What are De-cap cells ?

Decap cells are normal capacitors added in the design between the power and ground rails to overcome the effect of dynamic IR drop. At the active edge of the clock most of the sequential cells starts switching simultaneously and consumes huge current for small interval of time. If the flop is placed away from the power source then there is a chance that flop will not get the required voltage and goes to the metastable state. To overcome this effect we add decap cells over there.

What are filler cells ?

Filler cells are non functional cells used to maintain the n-well and p-well continuity also the power continuity. 

What are tie high and tie low cells ?

For the floating input pins of the standard cells we need to connect it to either VDD or GND, so insted of connecting them directly to VDD and GND power rings we use special kind of cells, those cells are called tie high and tie low cells. 

What are pad cells ?

In PCB the wire lengths are very large in mm and within the chip net lengths are very small which are in microns. So normal buffers cannot withstand huge loads, to overcome that a special kind of cells are used those we call it as padcells. Padcells are the combination of large buffers and level shifters.

What is pitch ?

When two metal routes are routed parallely following minimum spacing and minimum width rule, than the distance between the center of one route to another route is called as the pitch.

What is SITE?

One SITE is the smallest width standard cell and it is equal to the metal2 pitch.

QUESTIONS ON VLSI BASICS

QUESTIONS BASED ON FLOORPLANNING

What is core utilization ?

It is the ratio of (std cell area + macro area + blockage area) / total area

What is cell utilization ?

It is the ratio of std cell area/ total area allocated to standard cells

What is gate count?

Gate count is 3 to 4 times of instance count.

Total placeable instance area / 2 input NAND gate area in .lib

What is aspect ratio ?

It is the ratio of vertical routing resources to the horizontal routing resources.

What is a channel ?

It is the minimum spacing required between two macros or between macros and boundary.

How do you calculate the channel width ?

Based on the fly-line analysis we will able to know the no. of signals passing through the channel and suppose “21” signals are passing than “21” metal routes are required. So if the signal are need to be routed vertically than we divide the no of routes by no of vertical layers. Suppose no of vertical layers is “3”. On each metal layer 7 track are needed so the width of channel should be equal to 7 tracks.

How do you measure the no. of signals passing through a channel ?

Through the fly-line analysis

How do you calculate the the metal routes that can be passed through a channel ?

The no of metal routes required is equal to the no of signal passing through the channel

Guidelines for general macro placement ?

If two communicating macros placed close to each another and if all the pins of both the macros are connected to each other than there is no need of spacing but if some pins are talking with the core logic than we need to provide some spacing so that from the pin route should come and connect to the logic. So minimum spacing required between the 2 macros or boundary and macro is called as the channel.

What is Grid ? Diff kinds of Grid ?

Grids can be of manufacturing grid, placement grid and routing grid. The minimum metal length that can be manufactured is called manufacturing grid. Placement grid is nothing but one SITE whose height is equal to the std cell height and width is multiple of M2 pitch and all the cells are placed according to this grid. During routing tool divides entire area into small square boxes and assigns horizontal and vertical tracks to it and route according to these routing grids.

What is core area ?

The area in which standard cells, memories, blockages, power mesh, routing of nets are present we call it as core area

What do you mean ny a 9Track Cells ?

If there are 9 parallel routing tracks are present in a cell than we call it as 9 track cells.

Typical Metal layers used in Macro ?

Generally M1 to M4 metal layers are used by macros .

ENCOUNTER COMMANDS

To select all the ports in the design

selectIOPin * 

To display all the contents in the shell window

enc_tcl_return_display_limit value

To get the direction of ports

get_attribute  [get_pins *] direction

To get the output ports name

all_outputs

get_attribute [get_pins * -filter "direction==out"] name

To get the input ports name

all_inputs

get_attribute [get_pins * -filter "direction==in"] name

To filter weather a port is signal or clock port

To select all the instances in the design

selectInst *

To get the instance names in the design

get_cells *

get_cells * -hierarchical

get_attribute [get_cells * -hierarchical] hierarchical_name

To get all the net names in the design

get_nets *

get_nets * -hierarchical

To get all the combinational cells in the design

get_attribute [get_cells * -hierarchical -filter "is_combinational==true"] hierarchical_name

To check weather a cell is combinational or not

get_attribute [get_cells tem_mbist4/l_releasclk_reg/g16] is_combinational

To get all the sequential cells in the design

get_attribute [get_cells * -hierarchical -filter "is_sequential==true"] hierarchical_name

get_attribute [get_cells tem_mbist4/l_releasclk_reg/g16] is_sequential

To get the no. of pins of an instance

get_attribute [get_cells tem_mbist4/l_releasclk_reg/g16] pin_count

To get the library cell name of an instance

get_attribute [get_cells tem_mbist4/l_releasclk_reg/g16] ref_lib_cell_name

To get only sequential cells excluding memories

get_attribute [get_cells * -hierarchical -filter "is_memory_cell==false && is_sequential==true"] hierarchial_name

QUESTIONS ON LOW POWER

What is isolation cell ?

The cells which are used to isolate the output of the power down domain is called isolation cells.

Why output of the power down domain is isolated ?

The signals of the power down domain reaches to some intermediate values due to power gating effect and if those signals are fed to the power up domain, than it will effect the functionality of the power up domain. So to avoid that we isolate the outputs of the power down domain.

What is crowbar current?

When a particular power domain is shut down than outputs of it reaches to some intermediate vales due to the power gating effect and when it is feed to the power up domain inputs than it results in the crowbar current.

What is isolation enable signal ?

Isolation enable signal decides when the output of the power down domain should be isolated.

What kind of cells are used for isolation?

For clamp "0" we used AND gate and for clamp "1" we use OR gate.

What is level shifter ?

When we want to shift a signal from one voltage level to another than we use level shifter. Level shifters are generally used in the multiple voltage designs.

What is AON cells ?

When there is a power domain which is at shutoff condition and some logic of that domain on need to be "ON" at that particular time than we use always on cells in that case. AON cells have two power supplies one is primary and another is secondary.

What are power switches ?

The switches that are used to shutoff the pull up or pull down network when the design is not in functional, than we call it as power switches.

What is power gating ?

The technique in which either pull up or pull down network is shutoff with the help of switches, than we call it as power gating mechanism.

What is coarse grain and fine grain power gating techniques ?

In fine grain power gating technique, for each cell we use one power switch and in coarse grain for bunch of cells one power switch is used.

In fine grain technique cell density is more so generally it is not preferred and coarse grain technique is used widely.

What is rush current ?

When a power domain is in shutoff condition and it is powered on suddenly, than all the internal capacitors start to charge simultaneously and huge charge is drawn which leads to the rush current.

What is ramp up time ?

The time by which a shut down domain is powered up is called ramp up time.

What is header and footer switches ?

The power switch which is used to gate the VDD we call it as header switch and the switch which is used to gate the VSS than we call it as footer switch.

What happens if we will not use level shifter in multi voltage designs ?

If the voltage given to the input of the transistor exceed the breakdown voltage, than the dielectric layer damages. Breakdown voltage is very large than the supply voltage. So in a multi voltage design when there is a signal propagating from high to low voltage domains, then it may lead to breakage of the dielectric layer if that voltage exceeds the breakdown voltage. When a signal is propagating from lower to higher voltage domains, than it may happen that this low voltage cannot exceed the threshold voltage, in that case transistors will not become on and it will affect the functionality. To avoid that that we use high to low level shifter and low to high level shifters.

What is Intra polation ?

When the tran and cap values lies whithin max limit but not exactly the values present in the table, than tool tries to calulate it to the nearest possible value. This process is called intrapolation.

What is Extrapolation ?

When the tran and cap values lies above the max limit than tool tries to map it the highest value in the look up table, this process we call it as extrapolation. With this process as the delay values calculated are less as compared to the actual delays, tool falsely meet the setup timing.

OTHER IMPORTANT QUESTIONS

What are the contents of tech lefs ?

Metal layer information

Metal layer directions

Via information

Antenna ratio

r/l and c/l information

What are the contents of standard cell lefu ?

Pins information

Obstructions

What are the types of captables ?
Normal captables
Advanced captables

Difference between normal and advanced captables ?
In normal captables resistance and capcitance per unit length information is present and in advanced captables resistance and capacitance per unit length is present in terms of 3D format .

What are the types of blockages ?
Soft blockage
Hard blockage
Partial blockage or density screens

What is the difference between the fence, guide and region ?

Fence : If we have different modules defined in the netlist, then they are preferred to keep in a specified area where we don't want to keep other module cells. By creating fence tool will not allow other cells to place inside it and will not allow the logic related to fence to place outside of it.

Guide: By creating guide there is a flexibility of moving the cells in and out of the design area.

Region: Other group cells can be moved into the region but region cells cannot move outside of the region.

How tool perform the signal routing ?

Generally routing occurs in 3 steps i.e track assignment, global routing and detail routing.

What router is used by encounter and icc2 ?

Encounter tool uses SMART router and icc2 uses ZRouter.

What are bond pads and bond wires ?

Bond pads are metal sheets and bond wires are used to connect the package pins to the bond pads and bond pads to the IO pads.

Why bond pads are used ?

External environment wire's thickness is more so it can directly connect to the IO pads as it will not fit so these external wires connects to the bond pads and than to the IO pads.

What are double cut vias and advantage of it ?

When a single via is divided into two than we call it as double cut via and with these vias yield increases because during manufacturing if through one via connection fails than through other via connection can be made.

What are attach IO buffers and why these are used ?

These are nothing but the buffers added near to the ports inside the block to meet transition at the top level.

Why end cap cells are added in the design ?

During manufacturing etching is done and during that process cells present in the boundaries are etched, so with that functional cells are affecting and it may leads to change of behavior of the cells. So to avoid this problem end caps are added in the boundaries.

DRC & LVS

What are the inputs for DRC and LVS ?

DRC: GDS file, drc rule deck 

LVS: HCELL, CDL libs, source and layout netlist

What is HCELL ?

It contains all the cells of source and layout netlist. Suppose in our design 100 NAND gates are present than no need to process all those and one NAND gate is enough. So all those cells information is there in the HCELL file.

What are CDL libs ?

CDL libs are circuit design level libs used to extract the transistor level description of all the gates.

CROSSTALK

What is crosstalk ?

When signal switching on one net causes the unwanted changes in the nearby net and leads to either increase or decrease in delays than we call that effect as crosstalk.

How crosstalk can be avoided ?

By insertion of buffer so that parallel net lengths can be decreased

By switching the metal layers

Minimizing the parallel length wires

By shielding

Giving more spacing between the nets

CAPACITANCE

What are the types of capacitances present?

Area capacitance

Fringing capacitance

Coupling capacitance