TIMING

What is the setup and hold time requirement of a flop?

Setup: It is the time , valid and stable data should be present at the input data pin of the flop before the clock edge occurs.

Hold: It is the time, valid and stable data should be present at the input  data pin of the flop after the clock edge occurs.

If top level transition is met without adding the attach IO buffer than also it is advisable to use these buffers, why ?

Because the sloppy transition leads to crosstalk.

What happens if transition and loads are not mentioned for the input and output ports?

If min transition is not mentioned than tool takes it as zero and meet the timing in that particular by taking less delay but in reality there will be some transition value when we see it from the top level and same for the output load, if load is not mentioned than tool considers it as zero and analyze the timing in that path by taking the less delay.

What is setup and hold mantras ?

Setup:

Data launched at the current lunch edge should be captured at the current capture edge.

Hold:

The data launched by the current lunch edge shouldn't be captured by the previous capture edge.

The data launched by the next launch edge shouldn't be captured by the current capture edge.

Why sharper transition values are set in PNR?

To avoid crosstalk

To avoid short circuit current

To avoid electromigration

What is synchronizer ?

When a data signal is crossing different clock domains than synchronizer is used mainly in case of asynchronous clock domains.

What is single cycle behavior?

The data launched by the launch flop at the current lunch edge should be captured by the capture flop at the current capture edge. This we call as the single cycle behavior.

What is multi cycle behavior?

When data lunched by the launch flop at the current launch edge is captured by the capture flop at the n+1 capture edge where "n" is the current capture edge than we call this as multi cycle behavior.

What is metastability?

When signal at the input pin of the flop changes in the setup/hold window than output of the flop is unpredictable and we call it as metastability.

List out different optimization techniques ?

Logic restructuring

Upsize

Downsize

Pin swapping

Buffer insertion

What is manufacturing grid ?

The minimum length of a metal that can be manufactured is called the manufacturing grid ?

What is recovery and removal parameters in asynchronous clocks ?

Recovery: It is the time, the reset signal is maintained constant before the clock edge is applied.

Removal: It is the time, the reset signal is maintained constant after the clock edge is applied.

What is time borrowing ?

Let us consider there is a timing path in which path delay is 7ns and clock period is 5ns(considering setup requirement and all others as zero for latch), and subsequent timing path is having a path delay of 2ns with the same clock. Than to meet the first timing path it can borrow 2ns of delay from the second timing path. This concept we call it as time borrowing.