OTHER IMPORTANT QUESTIONS

What are the contents of tech lefs ?

Metal layer information

Metal layer directions

Via information

Antenna ratio

r/l and c/l information

What are the contents of standard cell lefu ?

Pins information

Obstructions

What are the types of captables ?
Normal captables
Advanced captables

Difference between normal and advanced captables ?
In normal captables resistance and capcitance per unit length information is present and in advanced captables resistance and capacitance per unit length is present in terms of 3D format .

What are the types of blockages ?
Soft blockage
Hard blockage
Partial blockage or density screens

What is the difference between the fence, guide and region ?

Fence : If we have different modules defined in the netlist, then they are preferred to keep in a specified area where we don't want to keep other module cells. By creating fence tool will not allow other cells to place inside it and will not allow the logic related to fence to place outside of it.

Guide: By creating guide there is a flexibility of moving the cells in and out of the design area.

Region: Other group cells can be moved into the region but region cells cannot move outside of the region.

How tool perform the signal routing ?

Generally routing occurs in 3 steps i.e track assignment, global routing and detail routing.

What router is used by encounter and icc2 ?

Encounter tool uses SMART router and icc2 uses ZRouter.

What are bond pads and bond wires ?

Bond pads are metal sheets and bond wires are used to connect the package pins to the bond pads and bond pads to the IO pads.

Why bond pads are used ?

External environment wire's thickness is more so it can directly connect to the IO pads as it will not fit so these external wires connects to the bond pads and than to the IO pads.

What are double cut vias and advantage of it ?

When a single via is divided into two than we call it as double cut via and with these vias yield increases because during manufacturing if through one via connection fails than through other via connection can be made.

What are attach IO buffers and why these are used ?

These are nothing but the buffers added near to the ports inside the block to meet transition at the top level.

Why end cap cells are added in the design ?

During manufacturing etching is done and during that process cells present in the boundaries are etched, so with that functional cells are affecting and it may leads to change of behavior of the cells. So to avoid this problem end caps are added in the boundaries.