What are the inputs for DRC and LVS ?
DRC: GDS file, drc rule deck
LVS: HCELL, CDL libs, source and layout netlist
What is HCELL ?
It
contains all the cells of source and layout netlist. Suppose
in our design 100 NAND gates are present than no need to process all
those and one NAND gate is enough. So all those cells information is
there in the HCELL file.
What are CDL libs ?
CDL libs are circuit design level libs used to extract the transistor level description of all the gates.
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