SYNTHESIS
Input files required for synthesis
- RTL
- SDC
- .LIBS
Output files of synthesis
- gate level netlist
- SDC
PNR
Input files required for PNR
- Gate level netlist
- sdc
- upf/cpf
- .libs
- .lefs
- captables
Outputs of PNR
- Gate level netlist
- sdc
- def
- lef
- database
EXTRACTION
Input files required for extraction
- .def
- qrc tech file
Outputs of extraction
- spef
CROSSTALK
Input files required for crosstalk
- netlist
- sdc
- spef
Outputs of crosstalk
- sdf
STA
Input files required for STA
- Netlist from PNR
- sdc
- .libs
- spef
- sdf
- .def
- .upf
- eco_spacing_rule file
Outputs of STA
- timing reports
LEC
Input files required for LEC
- golden netlist : netlist that we get from synthesis
- source netlist: netlist we got after PNR
- libs
Outputs for LEC
- comparison reports
DRC
Input files required for DRC
- GDS
- drc rule deck file
Outputs of DRC
- Reports
LVS
Input files required for LVS
- hcell
- cdl
- source netlist
- layout netlist
Outputs for LVS
- reports
thanks good information can u give every stage inputs and out of PD in detail which will become more helpful information means for floorplan,powerplan,placement,cts,routing stages
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