CONTENTS OF CTS SPEC

• Clock information for which clock tree need to build
• NDR rules (double width and double spacing)
• Max clock cap limit
• Clock inverters and buffers types
• Target skew
• Preferred routing layers
• Non leaf pin max tran
• Leaf pin max tran
• Max fanout
• Max delay
• Min delay

INPUTS AND OUTPUTS OF EACH STAGE

SYNTHESIS

Input files required for synthesis

• RTL
• SDC
• .LIBS

Output files of synthesis

• gate level netlist
• SDC

PNR

Input files required for PNR

• Gate level netlist
• sdc
• upf/cpf
• .libs
• .lefs
• captables

Outputs of PNR

• Gate level netlist
• sdc
• def
• lef
• database

EXTRACTION

Input files required for extraction

• .def
• qrc tech file

Outputs of extraction

• spef

CROSSTALK

Input files required for crosstalk

• netlist
• sdc
• spef

Outputs of crosstalk

• sdf

STA

Input files required for STA

• Netlist from PNR
• sdc
• .libs
• spef
• sdf
• .def
• .upf
• eco_spacing_rule file

Outputs of STA

• timing reports

LEC

Input files required for LEC

• golden netlist : netlist that we get from synthesis
• source netlist: netlist we got after PNR
• libs

Outputs for LEC

• comparison reports

DRC

Input files required for DRC

• GDS
• drc rule deck file

Outputs of DRC

• Reports

LVS

Input files required for LVS

• hcell
• cdl
• source netlist
• layout netlist

Outputs for LVS

• reports

PHYSICAL DESIGN FLOW

Below are the basic steps of PNR flow:                                                       

Import:  All design related inputs like "Gatlevel netlist, .libs, .lefs, SDC, UPF/CPF" are read by the tool. We perform sanity checks like check_design and check_timing to know the netlist and DSC related issues. At this stage we need to check that timing is compare able with the synthesis results.

Floor planning: Based on the flyline analysis macros are arranged towards the boundary of the design. We also add blockages like soft, hard and partial blockages or density screens to ease the congestion.

Power planning: Power mesh is build by using the top metal layers on the entire design.

Pre-placement: At this stage tap cells, power switches are placed.

Placement: Actual placement of standard cells is done.

Post placement optimization: Optimizations are done like upsizing, buffer insertion, fanout splitting to meet setup, tran and cap violations.

Clock tree building: On clock path buffers are inserted in such a way that skew is minimized and latency is within the target.

Post clock tree optimization: Once clock tree building is done setup timing may impact due to skew changes and as actual clock nets routing is done, it may results in clock tran and cap. After CTS we check hold timing as well. So tool does optimization of the cells to meet setup, hold, tran and cap.

Signal routing: At this stage actual signal routing is done and basically it happens in three stages like track assignment, global routing and detailed routing.

Post routing optimization: After actual signal routing net lengths increases so it may results in the timing violations. So again timing optimization is done at this stage.

Standard cell filling: In this stage std cell fillers are added in the entire design

Metal fill: Metal pieces are added at this stage to avoid the min and max density violations.